1. Field of the Invention
The present invention is generally related to a method for operating a memory device, and particularly to a method for operating a nitride read only memory device (referred as to NROM hereinafter).
2. Description of Related Art
Conventional NROM devices usually comprise of a oxide-nitride-oxide (ONO) stacked layer structure as the electron trapping layer, a gate is located above the ONO layer, and a source and drain neighbor to the gate located in the substrate. Due to the fact that the material of the electron trapping layer is mainly nitride, a device which allows electrons migration and electrically erasable programmable ROM is named as NROM.
The nitride layer has electron trapping properties causing the electrons that are injected into the nitride layer cannot be evenly distributed in the nitride layer but instead are gathered into a specific region of the nitride layer. Therefore when programming the NROM device, the electrons tend to accumulate in the channel near the source and above the drain. By varying the bias voltage of the source and drain next to the gate, a single nitride layer can accommodate two different groups of electrons. The nitride layer can contain two different groups of electrons, just one group of electrons, just an empty group, or a combination. As a result, the NROM device can have 4 different stages in one single cell known as a 1 cell 2 bit flash memory.
The size of semiconductor components are shrinking due to component integration and the advancement in technology. As a result, the line width of the gate of a NROM device also decreases to such a level that the operation of the NROM device is affected because a large current is required for programming. The problem is especially adverse when erasing the NROM device because the electrons injected into the channel near the source and above the drain cause a large amount of holes after repeated erasing of the cell. These holes will cause serious leakage in cells which share the same bit-line and word-line, especially under high temperature causing an effect known as over-erase. Furthermore if the initial voltage is lowered or the channel length is reduced, the above leakage problem becomes more severe.
The present invention provides a method for operating a NROM device to prevent the large number of holes located near the source and above drain causing serious leakage on the electrons of the neighbor bit-line.
The present invention provides a method for operating a NROM device for lowering the current required for channel hot electron injection (CHEI).
The present invention provides a method for operating a NROM device, where the source and drain are surrounded by a heavily doped substrate. When programming the NROM device, a more positive source bias and a more negative substrate bias is used to increase the body effect of the substrate for reducing the current required for Channel Hot Electron Injection (CHEI) programming. Furthermore, before the first erase operation is performed on the NROM array, a pre-programming operation is performed to program every single memory cell of the NROM array to the written state for preventing over-erasing of the memory cells.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.